Phase-locked loop (“PLL”) circuits are found in many processing systems. They are, for example, commonly used to generate mixing signals in communications systems and clock signals for controlling the speed and synchronizing the operation of various components in microprocessor systems.
The structure of a PLL is generally well known in the art. FIG. 1 is an example of a prior art PLL circuit. With reference to FIG. 1, one common component of a prior art PLL 5 is a voltage controlled oscillator 25. The voltage controlled oscillator 25 (“VCO”) may be a voltage controlled crystal oscillator (“VCXO”), a surface acoustical wave (“SAW”) filter controlled oscillator, or other known oscillator in the art. The fundamental frequency of the VCO as established by the crystal or SAW filter may be adjusted or pulled in proportion to an input voltage signal VIN. Thus, the frequency of the output timing signal Fout may be modified in response to changes in the level of the input voltage signal VIN. The input reference signal Fref is the timing reference signal either embedded in the transport signal or provided by an integrated timing supply known in the art, e.g., an accurate oscillator signal transferred independently of the transport signal to achieve synchronicity. A phase-frequency detector 10 may receive the input reference signal Fref and a feedback form of the output timing signal Fout. Fref and the feedback form of Fout may be compared to determine the phase and frequency equivalence of Fref and the feedback form of Fout. The phase-frequency detector 10 has an output UP indicating that the phase-frequency of the VCO 25 requires adjustment to increase the frequency of Fout. The second output DOWN of the phase-frequency detector 10 indicates that the VCO 25 requires adjustment to decrease the frequency of Fout. The output signal UP and DOWN of the phase-frequency detector 10 may be provided as inputs to a charge pump 15. The charge pump 15 provides an output current ICP that is proportional to the desired frequency of Fout. ICP may then be provided to a low pass filter 20. The low pass filter 20 removes any undesired high frequency noise components that may be generated in the phase-frequency detector 10 or the charge pump 15 and creates the input adjustment voltage VIN for the VCO 25.
As is known in the art, the frequency of Fref may be a submultiple of the frequency of Fout. If such is the case for the design of the prior art PLL as illustrated, a frequency divider 30 may be optionally placed in the feedback path of Fout. The frequency divider 30 divides the frequency of Fout such that Fref is compared with a feedback signal that is a submultiple of Fout.
FIG. 2 is a diagram of outputs of the phase-frequency detector and input reference signals of the prior art phase locked loop of FIG. 1. With reference to FIG. 2, the outputs UP and DOWN of the phase-frequency detector 10 are generally digital signals. In this example, the phase frequency detector 10 determines phase and frequency synchronicity at the fall 30, 35, and 40 of the input reference signal. During the time period A, if the phase and frequency of Fout and Fref are aligned, the signal UP and the signal DOWN possess an equal pulse width. As shown during time period B, if the phase of Fout lags or the frequency is lower than Fref, the signal UP has a pulse width longer than the signal DOWN. If the phase of Fout leads or the frequency is higher than Fref, the signal DOWN has a pulse width longer than the signal UP. The charge pump 15 responds appropriately to create the necessary current, ICP, which, when filtered, creates the input voltage VIN to adjust the VCO 25.
Determination of phase-frequency lock of PLLs is important for the functioning of circuits that are to receive and extract the data from the transport signal. Generally, the circuits provide lock notification signals indicating that the phase lock loop is in phase-frequency synchronization. U.S. Pat. No. 6,215,834 (McCollough), U.S. Pat. No. 5,886,582 (Stansell), U.S. Pat. No. 5,870,002 (Ghaderi, et al.), U.S. Pat. No. 5,838,749 (Casper, et al.), U.S. Pat. No. 5,822,387 (Mar), U.S. Pat. No. 5,724,007 (Mar), U.S. Pat. No. 4,499,434 (Thompson), and U.S. Pat. No. 5,394,444 (Silvey, et al.) are illustrative of circuits and systems that provide a notification of the phase-frequency synchronization. However, these notifications are limited to frequency error, loss of lock or loss of phase synchronization
Thus, a continuing need exists in the art to permit a quality of lock detection in PLL circuits.